1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit which operates so as to accept input signals in synchronization with a clock signal.
2. Description of the Related Art
In general, semiconductor integrated circuits are broadly classified into logic LSIs, such as a microcomputer, and memory LSIs, such as a DRAM. The microcomputer has been widely known as a semiconductor integrated circuit which operates in synchronization with a clock. On the other hand, in the memory LSIs, an SDRAM (Synchronous DRAM) or the like operating in synchronization with a clock has been developed.
In the SDRAM, an interfacing circuit is operated at high speed in synchronization with a clock signal supplied from the exterior of the SDRAM, so that writing or reading data at high speed is made possible while timing margins are kept.
FIG. 1 shows the block diagram of an input interfacing circuit 1 in the semiconductor integrated circuit of this kind. The input interfacing circuit 1 includes a clock buffer 2, a plurality of input buffers 3a, 3b, 3c, and a plurality of input signal accepting circuits 4a, 4b, 4c. Each of the input signal accepting circuits 4a, 4b, 4c includes a latch 5. The clock buffer 2 is supplied with a clock signal CLK from the exterior of a chip. This clock buffer 2 decides the signal level of the clock signal CLK, converts the clock signal CLK into an internal clock signal CLKIN of high level or low level, and outputs the internal clock signal CLKIN to the respective input signal accepting circuits 4a, 4b, 4c. The input buffers 3a, 3b, 3c are respectively supplied with input signals S1, S2, S3 from the exterior of the chip. These input buffers 3a, 3b, 3c decide the signal levels of the input signals S1, S2, S3, convert the input signals S1, S2, S3 into internal signals SIN1, SIN2, SIN3 of high level or low level, and output the internal signals SIN1, SIN2, SIN3 to the input signal accepting circuits 4a, 4b, 4c, respectively. The latches 5 accept the internal signals SIN1, SIN2, SIN3 in synchronization with the edge of the internal clock signal CLKIN, and output accepted signals SIN1A, SIN2A, SIN3A to a controlling circuit 6, or the like within the chip, respectively. In the figure, lines indicated by arrows denote wiring patterns, and the directions of the arrows denote the directions in which the signals are transmitted.
In the input interfacing circuit 1 described above, ordinarily the input buffers 3a, 3b, 3c are arranged near pads for receiving the signals from the exterior of the chip and are dispersed on the chip. In contrast, the input signal accepting circuits 4a, 4b, 4c are arranged at the predetermined position on the chip. Therefore, the wiring patterns which are respectively laid to transmit the internal signals SIN1, SIN2, SIN3 between the input buffers 3a, 3b, 3c and the input signal accepting circuits 4a, 4b, 4c can not have the same lengths. By way of example, the wiring pattern for transmitting the internal signal SIN1 is the shortest, and the wiring pattern for transmitting the internal signal SIN3 is the longest. Since the propagation delay time of each signal is proportional to the length of the wiring pattern, the internal signals SIN1, SIN2, SIN3 are respectively supplied to the input signal accepting circuits 4a, 4b, 4c at timings different from one another.
As a result, the timings of the respective latches 5 for accepting the internal signals SIN1, SIN2, SIN3 shift as shown in FIG. 2. In the example of FIG. 2, the signal in which a timing margin for a set-up time tS is the smallest is the internal signal SIN3, and the signal in which a timing margin for a hold time tH is the smallest is the internal signal SIN1. Here, the xe2x80x9cset-up time tSxe2x80x9d is the specification of the minimum time in which the input signal needs to be settled before the rise of the clock signal CLK, and the xe2x80x9chold time tHxe2x80x9d is the specification of the minimum time in which the input signal needs to be held after the rise of the clock signal CLK. Besides, in general, the ratings of external input terminals for the set-up time tS and the hold time tH are specified by the worst value of all input signals. For this reason, when the accepting timings of the internal signals SIN1, SIN2, SIN3 fluctuates, the timing margins of the external input terminals for the set-up time tS and the hold time tH become short.
The specifications of the set-up time tS and the hold time tH need to be made more strict as the frequency of the clock signal CLK becomes higher. In the SDRAM of high speed operation, therefore, the input signal accepting circuits 4a, 4b, 4c are respectively furnished with delay circuits 7a, 7b, 7c on the input sides of the latches 5 as shown in FIG. 3, thereby to lower the fluctuation of the timings of the internal signals SIN1, SIN2, SIN3. In the figure, the sizes of the delay circuits 7a, 7b, 7c express the lengths of delay times. The delay circuits 7a, 7b, 7c are respectively adjusted in accordance with the delays of the internal signals SIN1, SIN2, SIN3 attributed to the unequal lengths of the wiring patterns, and the timings at which the internal signals SIN1, SIN2, SIN3 are respectively transmitted to the latches 5 are set same. In consequence, the set-up times tS and hold times tH of all the internal signals SIN1, SIN2, SIN3 are equalized.
Meanwhile, in an SDRAM or the like, the combinations of the signal levels of a plurality of input signals received in synchronization with a clock signal CLK are decided as a plurality of controlling commands, by which an internal circuit is controlled.
As shown in FIG. 4, the input interfacing unit 1 of the SDRAM of this type is formed with a decoder 8 which receives accepted signals SIN1A, SIN2A, SIN3A output from respective latches 5, and which outputs a command signal CMD.
With the circuit shown in FIG. 4, the output of the command signal CMD delayed because the internal signals SIN1A, SIN2A, SIN3A accepted by the corresponding latches 5 are decoded by the decoder 8. As a result, the operation of a controlling circuit 6 delays, and an access time, or the like cannot be enhanced. In order to quicken the output of the command signal CMD, internal signals SIN1, SIN2, SIN3 before being accepted by the latches 5 should be decoded.
Each of FIGS. 5 and 6 shows the construction of the principal parts of an input interfacing unit 1 which serves to decode the internal signals SIN1, SIN2, SIN3 before being accepted by the latches 5, and which has been thought out by the inventors of the present invention.
The input interfacing unit 1 shown in FIG. 5 is formed with a command accepting unit 9 which includes a decoder 10, a delay circuit 7d and a latch [circuit] 5. The decoder 10 receives the internal signals SIN1, SIN2, SIN3, and outputs a command signal CMD to the delay circuit 7d. The delay circuit 7d outputs the delayed command signal to the latch 5. The latch 5 accepts the delayed command signal CMD in synchronization with an internal clock signal CLKIN, and outputs the accepted signal to the controlling circuit 6 as a command signal CMD1. Here, the delay circuit 7d is a circuit for adjusting the timings of the command signal CMD and the internal clock signal CLKIN which are supplied to the latch 5.
The input interfacing unit 1 shown in FIG. 6 is formed with a command accepting unit 11 which includes delay circuits 7e, 7f, 7g, a decoder 10 and a latch 5. The decoder 10 receives the internal signals SIN1, SIN2, SIN3 through the delay circuits 7e, 7f, 7g, respectively, and outputs a command signal CMD to the latch 5. The latch 5 accepts the command signal CMD in synchronization with an internal clock signal CLKIN, and outputs the accepted signal to the controlling circuit 6 as a command signal CMD1.
It is added that the input interfacing units 1 shown in FIGS. 5 and 6 are not known yet.
With the input interfacing unit 1 shown in FIG. 5, the command signal CMD has its width W narrowed by the decoder 10 as shown in FIG. 7. This incurs the problem that the timing margins of the command signal CMD for the set-up time tS and the hold time tH become small in the latch 5.
An object of the present invention is to provide a semiconductor integrated circuit which can reliably receive input signals without enlarging the circuit scale.
Another object of the present invention is to provide a semiconductor integrated circuit where an internal circuit can be quickly and reliably operated.
Still another object of the present invention is to set an optimal delay time of an input signal.
According to one of the aspects of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a delay circuit and a plurality of receiver circuits. The input signal supplied from the exterior of the integrated circuit is delayed for a predetermined length of time by the delay circuit, and then it is distributed and output to the plurality of the receiver circuits. The delay time of the delay circuit is set so that a receiving timing of an input signal received in synchronization with a clock signal is optimized in each of the receiver circuits. Each receiver circuit reliably receives the delayed input signal respectively in synchronization with a clock signal.
Therefore, it is unnecessary to provide a delay circuit in each of the plurality of receiver circuits. As a result, the plurality of receiver circuits can reliably receive the input signals without enlarging the circuit scale. When there is a need to adjust the delay time of the input signals, only one of the delay circuits needs to be changed.
Generally, in the semiconductor integrated circuit, the delay circuit is constructed by combining a resistor and a capacitor whose sizes are designed according to the lengths and the sizes of wirings, diffusion layers and insulators. This often results in the enlargement of the layout size of a delay circuit as compared to other circuits. The present invention makes it possible to reduce the number of the delay circuits so that the size of each delay circuit can be also be reduced as well as the size of the chip.
According to another aspect of the semiconductor integrated circuit in the present invention, switching the ON/OFF state of a switch provided in the delay circuit enables the transmission path of the input signal to change and its delay time to be adjusted. Therefore, when it is necessary to adjust the delay time of the input signal, only the switch needs to be changed.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a plurality of delay circuits, a plurality of receiver circuits, and an operating circuit. The delay circuit receives a plurality of input signals, and respectively outputs each of the delayed input signals to the plurality of receiver circuits. The receiver circuit receives the delayed input signals in synchronization with a clock signal. More than one of the delayed input signals are supplied to the operating circuit to perform a logic operation. The delay time of each delay circuit, for example, is set in accordance with the supplying timing to the input signal supplied to the operating circuit. As a result, the operating circuit performs the logic operation with a sufficient timing margin, and the timing margin between the input signals supplied to the operating circuit does not fluctuate, even when the delay time of each delay circuit is relatively shifted. By relatively shifting the delay time of each delay circuit, each receiver circuit becomes capable of reliably receiving the delayed input signal respectively in synchronization with a clock signal. Consequently, the delay circuit is able to supply input signals to both the operating circuit and the receiver circuit at an optimal timing.
According to another aspect of the semiconductor integrated circuit in the present invention, the logical operating circuit is constructed as a command decoder and it comprises a command signal receiver circuit, which receives a command signal output from the command decoder in synchronization with a clock signal.
The command decoder directly receives the input signals delayed by the delay circuits and outputs a command signal controlling the operations of internal circuits. The command signal receiver circuit reliably receives a wide command signal output from the command decoder in synchronization with a clock signal. Since the command signal receiver circuit receives the command signal decoded by the command decoder, an early start can be made in the operations of the internal circuits. Besides, there can be a plurality of command decoders and there can be a common delay circuit between the command decoders, so that the number of the delay circuits is further reduced to also reduce the size of each delay circuit as well as the size of the chip.
According to another aspect of the semiconductor integrated circuit in the present invention, switching the ON/OFF state of the switch enables the transmission path of the input signal to change and its delay time to be adjusted. Therefore, the optimal delay time of the each delay circuit can be set. When it is necessary to adjust the delay time of the input signal, only the switch needs to be changed. The layout data of the elements of the delay circuit other than the switch is made common between each other, so that the layout designing time may be shortened.
The delay time of the each delay circuit is adjusted so that the supply timings to the command decoder are equal between each input signal. This prevents the pulse width of the command decoder from becoming narrower so that the internal circuits can be reliable operated.